A generalized view of a computer system network is shown in FIG. 5 where a processor 14 has an internal processor bus 14b which communicates with a cache memory 19. Further, the processor 14 and cache memory 19 can communicate through an interface 20 to a system main memory 40 by means of a system bus which may be a dual system bus having two a busses 22a and 22b. Whenever the processor 14 needs data from memory, the cache memory 19 is the first line of resource for this data. An efficient cache design will, on average, contain the desired information for the processor about 90% of the time. If the cache memory 19 does not have the required information in its latest most valid state, then the data must be accessed from the system main memory 40 over a system bus mechanism such as the dual system busses 22. This latter cycle of retrieval from main memory of course, is much slower in time than the preferred case of retrieval from the cache memory 19 when there is a "cache hit" occurring.
FIG. 6 is a more detailed view of the cache memory design which indicates the elements of the cache memory module 19. Shown therein is the processor bus 14b which involves two busses. These include an address bus 14ba and a data bus 14bd. The cache module 19 is indicated as having three major units which include the Tag RAM unit 19t, a Data RAM unit 19d and a cache control module 16. The Tag RAM unit 19t holds the addresses of the data which is contained within the Data RAM 19d at any particular moment. The Tag RAM 19t provides the means by which there can occur a comparison of the processor requested address values with the address values held in the Tag RAM 19t. When a match occurs, this is called a "cache hit" and it indicates that the cache unit does indeed contain valid data for the requested address from the processor 14.
The Data RAM unit 19d in FIG. 6 is the storage area for all of the data that is held within the cache module 19 at any given moment. The Data RAM is generally a very expensive, very fast RAM device that can return data to the processor 14 during "cache hit" conditions. The Cache Control Unit 16 monitors the Tag RAM "hit" condition and also controls the reading out of the Data Ram 19d. When there is a Tag "miss" condition (not a hit), then the Cache Control Unit 16 controls the writing of data into the Data RAM 19d which data has been subsequently retrieved from the main memory 40. The activity for retrieving data, after a miss, from main memory 40 and writing this into the cache 19 is called "filling" (loading) the cache.
In order to gain higher cache "hit" rates, that is to say, 90% and above, it has been found that a special structuring of the cache data into several groups or banks of data is a very effective arrangement. These groups or banks of data are often referred to as "sets" or as "ways".
FIG. 2 is a drawing which illustrates the Tag units and Data RAM units as separate sets or ways and illustrates this as a four-set type of cache structure. Here the Data RAM 19d is constituted of four separate data groups or sets, 19d0, 19d1, 19d2, and 19d3. For a 64K word cache, the data will then be grouped into four cache sets each of which holds 16k words. However, only one of the four cache sets will contain the data for any given address in the Tag RAM 19t, at any given time. Thus for a cache "hit", only one of the four sets of the Data RAM 19d will be enabled to drive data onto the bus 14bd, FIG. 2, back to the processor 14.
Each of the cache sets has its own individual Tag RAM unit 19t. In FIG. 2, there are four Tag RAMs shown as 19t0, 19t1, 19t2, and 19t3. Each of these four Tag RAMs will hold 4K addresses. Each Tag RAM set is a 4K Tag RAM since each of the 4,000 addresses it contains actually points at a four-word block unit (w1, w2, w3, w4) within the Data RAM 19d. With the multiple sets (four sets illustrated here), there is only one set that is allowed to contain a given address value and to therefore produce a "hit" condition at any given time. The Tag set that produces the "hit" will select its associated Data RAM 19d in order to drive data to the processor 14, on bus 14bd
Since the cache memory 19 is structured into various identical portions called sets or ways, it is seen that the cache memory may be capable of operation under various combinations of usage of these sets or ways where some sets may be operative and some sets may be inoperative at any given time. It is this configuration of the combination of the cache sets that is the general focus of the system described in this disclosure.
It is an object of the present system to provide for control as to which configurations of data sets are to be used at any given time. It is also an object to provide for the automatic adjustment of the configuration of the cache sets under certain error conditions and also to provide for the continuing operation of the cache memory even when certain error-type transitions in the configuration may occur so that the cache memory can continue to operate in a degraded configuration without interruption to the processor.
Theory and experience indicates that the "larger" is the cache unit, the greater is its storage capacity and therefore the greater is its potential to assist the processor in providing immediate "hit" data. Thus, for a multiple set cache, such as the four-set cache used and shown herein, the maximum configuration whereby all cache sets are in "on-line" operation, provides the maximum performance. However, even though there are multiple cache sets, it is necessary to account for the possibility that less than the maximum number of sets in the configuration will be useable, such as for example, only three sets of the four being available at some given moment. These "less than maximum" type configurations might occur for several reasons which include (a) the intentional reduced configuration to provide a lower performance system for shipment; (b) the unintentional reduced configuration due to the occurrence of some error condition in one or more of the cache sets.
The presently described system will be seen to enable operator control and maintenance subsystem control of the cache-set configurations in addition to enabling operations of the system under an automatic adjustment arrangement even when certain error conditions reduce the usability of certain ones of the cache sets.